The present invention relates generally to semiconductor devices, and more particularly to silicon on insulator transistors.
Semiconductor devices such as transistors, resistors, capacitors, and other circuit elements, are formed in and upon semiconductor substrates. These circuit elements are interconnected by contacts and vias, which connect to patterned conductor layers which are separated by various dielectric layers.
A critical objective of the semiconductor industry has been to continually decrease the size of semiconductor devices to increase performance and reduce cost.
The ability to reduce performance degrading parasitic capacitances resulting from diffusion of junction dopants into semiconductor substrates has been accomplished through the use of silicon on insulator (SOI) technology. The SOI technology consists of forming the desired semiconductor devices in a layer of silicon, which overlies an insulator layer deposited on a conventional semiconductor substrate.
As semiconductor technology has advanced, there has been a continuing concentration on reducing the size of the semiconductor devices to allow for increased levels of circuit integration, improved performance, and higher density.
However, when the length and width of a semiconductor device are reduced, the length and width of the contacts connected to the semiconductor device must also be reduced. When the length and width of the contacts are reduced, the cross-sectional area is reduced by the square of the length or width and the resistance generally increases by the square (power of 2). The industry is currently reaching the point where the size is so small that the relative resistance is so high as to render connection to small devices impossible.
As devices continue to be reduced in size, it is clear that a breakthrough solution to this problem is required for continued success in reducing semiconductor device size and thus increasing device integration, performance, and function while at the same time reducing cost.
The present invention provides a semiconductor device in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide a smaller semiconductor device (transistor) footprint.
The present invention further provides a semiconductor device in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide a contact to silicon connection.
The present invention further provides a semiconductor device in which angled implantation of dopant is followed by formation of vertical trenches, which are also implanted with dopant. A rapid thermal anneal forms source/drain extension junctions in the semiconductor or the silicon on insulator substrate which are below the surface thereof to provide reduced junction parasitic capacitance.
The present invention further provides a semiconductor device in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide increased area vertical electrical connections between the contact and the silicon.
The present invention further provides a semiconductor device in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide a new method of forming contact to silicon connections.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.